Many of these details were uncovered from this thread on Discord:

• Discord - Group Chat That’s All Fun & Games

I’ll make good use of Dddaaannn’s final summary, and also copy/paste any other highlights we discover along the way.

Example Output

Summary

• PC: CPU program counter (16-bit)

• A: CPU Accumulator

• X: CPU X register

• Y: CPU Y register

• Z: CPU Z register

• B: CPU base page (B) register

• SP: Stack pointer (16-bit)

• MAPH + MAPL: The current MAP configuration

  • TODO: Let’s elaborate further on how to decipher this

• LAST-OP: The bytes of the last instruction performed by the CPU, in hex

• (?) In: "Instruction," a byte value, seems to always be 00

• P: CPU status register, in hex

• P-FLAGS: A rendering of the CPU status register, as NVEBDIZC

• (?) RGP: Four mysterious status bytes, as MRGP; dunno why the M isn't in the legend but there's space for it

• uS: Processor state, a byte described here: https://github.com/MEGA65/mega65-core/blob/master/src/vhdl/gs4510.vhdl#L858

• Notably, the monitor only uses the high byte of a 16-bit value for this, so I don't know how this translates exactly.

• (?) IO: Some kind of "I/O fast mode," either W for write, R for read, or - for none

• (?) ws: Wait states (plural), a byte described throughout gs4510.vhdl as wait_states

• h: Hypervisor mode, displayed as H for Hypervisor mode or - for user mode; observed to be when running Hypervisor code vs. MEGA65 ROM/RAM

• RECA8LHC: ROM banking flags that correspond to $D030, namely:

  • bit7: ROM E

  • bit6: character set ROM

  • bit5: ROM C

  • bit4: ROM A

  • bit3: ROM 8

  • bit2: palette ROM for colors 0-15

  • bit1: external genlock enable (possibly? unrelated to ROM banking?)

  • bit0: extended color RAM mapping into $DC00-$DFFF.

Digging for more details

• Much of the detail defining the behaviour of the r command in the uart monitor (used to display these register details) is defined in the following file:

  • mega65-core/src/monitor/monitor.a65 at development · MEGA65/mega65-core