{"type":"doc","content":[{"type":"extension","attrs":{"layout":"default","extensionType":"com.atlassian.confluence.macro.core","extensionKey":"toc","parameters":{"macroParams":{},"macroMetadata":{"macroId":{"value":"b843f7ac-cecb-41bc-b8be-c80570c7ef40"},"schemaVersion":{"value":"1"},"title":"Table of Contents"}},"localId":"e532231d-8b14-4f70-8eb1-30e7b1bcb893"}},{"type":"paragraph","content":[{"text":"This page came about after discussions in this discord thread:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"inlineCard","attrs":{"url":"https://discord.com/channels/719326990221574164/1045689070833119252/1117961151737757767"}},{"text":" ","type":"text"}]}]}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Mapping Mechanism Priority","type":"text"}]},{"type":"paragraph","content":[{"text":"The MEGA65 has 3 mapping mechanisms:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"HIGHEST PRIORITY","type":"text","marks":[{"type":"underline"}]},{"text":" = Register ","type":"text"},{"text":"$D030","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"for mapping in C65 ROM chunks","type":"text"},{"type":"hardBreak"},{"text":" ","type":"text"}]}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"LOWER PRIORITY","type":"text","marks":[{"type":"underline"}]},{"text":" = the “","type":"text"},{"text":"MAP","type":"text","marks":[{"type":"strong"}]},{"text":"” opcode mechanism","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"for more flexible mapping of ram/rom at a granularity of 8kb blocks","type":"text"},{"type":"hardBreak"},{"text":" ","type":"text"}]}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"LOWEST PRIORITY","type":"text","marks":[{"type":"underline"}]},{"text":" = Register ","type":"text"},{"text":"$01","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"for mapping in C64 ROM chunks","type":"text"}]}]}]}]}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Overall Memory Layout","type":"text"}]},{"type":"mediaSingle","attrs":{"layout":"center"},"content":[{"type":"media","attrs":{"width":637,"id":"8258d282-28e1-48c2-aa50-7d1220cdae62","collection":"contentId-33259521","type":"file","height":625}}]},{"type":"paragraph"},{"type":"heading","attrs":{"level":1},"content":[{"text":"Register $D030","type":"text"}]},{"type":"mediaSingle","attrs":{"layout":"wide","width":100.0},"content":[{"type":"media","attrs":{"width":1109,"id":"f9bc69c8-e0f6-45a0-9bf3-147625ebae4a","collection":"contentId-33259521","type":"file","height":233}}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"“MAP” instruction","type":"text"}]},{"type":"mediaSingle","attrs":{"layout":"center"},"content":[{"type":"media","attrs":{"width":731,"id":"9ce01274-544f-47f7-8705-8d456cbec29a","collection":"contentId-33259521","type":"file","height":505}}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"For ","type":"text"},{"text":"MAPL","type":"text","marks":[{"type":"strong"}]},{"text":", registers ","type":"text"},{"text":"X","type":"text","marks":[{"type":"strong"}]},{"text":" and ","type":"text"},{"text":"A","type":"text","marks":[{"type":"strong"}]},{"text":" will describe:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"A bitfield for which 8kb blocks to select","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"An 20-bit address offset (with lower 8-bits set to zero)","type":"text"},{"type":"hardBreak"},{"text":" ","type":"text"}]}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"For ","type":"text"},{"text":"MAPH","type":"text","marks":[{"type":"strong"}]},{"text":", registers ","type":"text"},{"text":"Z","type":"text","marks":[{"type":"strong"}]},{"text":" and ","type":"text"},{"text":"Y","type":"text","marks":[{"type":"strong"}]},{"text":" will describe:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"A bitfield for which 8kb blocks to select","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"An 20-bit address offset (with lower 8-bits set to zero)","type":"text"}]}]}]}]}]},{"type":"mediaSingle","attrs":{"layout":"wide","width":100.0},"content":[{"type":"media","attrs":{"width":868,"id":"3a308dfb-2659-40ae-81e9-ddcb29081dd9","collection":"contentId-33259521","type":"file","height":467}}]},{"type":"paragraph"},{"type":"paragraph","content":[{"text":"I.e.: when we look at the 'r' output for MAPL and MAPH:","type":"text"}]},{"type":"codeBlock","content":[{"text":"PC A X Y Z B SP MAPH MAPL LAST-OP In P P-FLAGS RGP uS IO ws h RECA8LHC\nE1B2 00 01 18 00 00 01F0 B300 E300 F0FA 00 22 ..E...Z. ...P 18 - 00 - ..c..lhc","type":"text"}]},{"type":"paragraph","content":[{"text":"You can interpret MAPH and MAPL as being:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"MAPH = (Z<<8) + Y","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"MAPL = (X<<8) + A","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"So if we wanted some assembly to enforce the mapping as described in the example values above, we could do:","type":"text"}]},{"type":"codeBlock","content":[{"text":"; prepare MAPL\nLDX #$00\nLDA #$E3\n\n; prepare MAPH\nLDY #$00\nLDZ #$B3\n\n; perform the mapping\nMAP\nNOP\n","type":"text"}]},{"type":"paragraph"},{"type":"codeBlock","content":[{"text":"physical_address = (((map_offset << 8) + cpu_address) & $FFFFF) | (megabyte_selection << 20)","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Register $01","type":"text"}]},{"type":"paragraph","content":[{"text":"$01 mapping is like counting from 0-3, adding one block each time: ","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"0: nothing mapped","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"1: map $D000 only","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"2: add KERNAL ROM","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"3: add BASIC ROM","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Bit 2 defines what to map at $D000 (0=CHARROM, 1=I/O)","type":"text"}]},{"type":"mediaSingle","attrs":{"layout":"wide","width":100.0},"content":[{"type":"media","attrs":{"width":982,"id":"049f28ed-d7da-4099-a524-3d7cf9615b27","collection":"contentId-33259521","type":"file","height":203}}]},{"type":"paragraph","content":[{"text":"NOTE","type":"text","marks":[{"type":"underline"}]},{"text":": Register $01 mappings aren’t quite as straightforward as these bit-fields suggest and have some ‘relationships’ with one another. For more info, assess the table here:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"inlineCard","attrs":{"url":"https://codebase64.org/doku.php?id=base:memory_management"}},{"text":" ","type":"text"}]}]}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"LGB’s mapping diagram","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Original","type":"text","marks":[{"type":"underline"},{"type":"strong"}]}]},{"type":"mediaSingle","attrs":{"layout":"wide","width":100.0},"content":[{"type":"media","attrs":{"width":2287,"id":"f2268302-bfe8-4b6f-8e4e-f2d0c3cb4512","collection":"contentId-33259521","type":"file","height":1030}}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"With annotations","type":"text","marks":[{"type":"underline"},{"type":"strong"}]}]},{"type":"mediaSingle","attrs":{"layout":"wide","width":100.0},"content":[{"type":"media","attrs":{"width":2046,"id":"9575dfd9-b35e-409e-aa88-9437a2a6a13e","collection":"contentId-33259521","type":"file","height":975}}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Examine mapping via 'm65dbg' tool","type":"text"}]},{"type":"paragraph","content":[{"text":"The latest contains a ","type":"text"},{"text":"mapping","type":"text","marks":[{"type":"code"}]},{"text":" command that provides a summary of all mapping mechanisms presently active.","type":"text"}]},{"type":"paragraph","content":[{"text":"More info on the “","type":"text"},{"text":"m65dbg","type":"text","marks":[{"type":"strong"}]},{"text":"” tool available here:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"inlineCard","attrs":{"url":"https://docs.google.com/document/d/1cEhHvvc1E47UgSoXvKPpwnf43l20sLPY-y-ZuQ4b_ng/edit"}},{"text":" ","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Example of use","type":"text","marks":[{"type":"underline"}]},{"text":":","type":"text"}]},{"type":"codeBlock","content":[{"text":"mapping\n\n$D030 register (highest priority)\n==============\n- $C000 <-- $2,C000 (C65 DOS chunk 3 + C65 KERNAL chunk 1 + CHARSET-C)\n- Selected C65 charset(?)\n\n\"MAP\" mechanism (lower priority)\n===============\nMAPL\n----\n- $2000 <-- $3,2000 (C65 BASIC chunk 1)\n- $4000 <-- $3,4000 (C65 BASIC chunk 2)\n- $6000 <-- $3,6000 (C65 BASIC chunk 3)\n\nMAPH\n----\n- $8000 <-- $3,8000 (C65 BASIC chunk 4)\n- $A000 <-- $3,A000 (C65 BASIC chunk 5)\n- $E000 <-- $3,E000 (C65 EDITOR + C65 KERNAL chunk 3)\n\n$01 register (lowest priority)\n===========\n- $A000 <-- $2,A000 (C64 BASIC)\n- $E000 <-- $2,E000 (C64 KERNAL)","type":"text"}]},{"type":"paragraph"},{"type":"paragraph","content":[{"text":"Here’s a comparison of the output while in BASIC 65 mode versus in MONITOR mode:","type":"text"}]},{"type":"mediaSingle","attrs":{"layout":"wide","width":100.0},"content":[{"type":"media","attrs":{"width":1247,"id":"5e2e4b04-e0ae-4a4d-96b4-f89eb9af67d1","collection":"contentId-33259521","type":"file","height":484}}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Excerpts from ‘memory-map.txt’ document","type":"text"}]},{"type":"paragraph","content":[{"text":"I’ll just copy/paste details from an old text file (the parts that I think are missing from this wiki page):","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"inlineCard","attrs":{"url":"https://github.com/gurcei/mega65-user-guide/blob/master/memory-map.txt"}},{"text":" ","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"We can clean up this page later and make it present better…","type":"text"}]},{"type":"paragraph"},{"type":"paragraph","content":[{"text":"Thoughts on this topic spawned from this thread:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"inlineCard","attrs":{"url":"https://www.forum64.de/index.php?thread/90784-map-instruction/"}},{"text":" ","type":"text"}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Possible location in the manual for this info:","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Possibly within \"Appendix G - 45GS02 Microprocessor\" - \"Extended Memory Support\" - \"Using the MAP instruction to access >1MiB\".","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"As this section's intention may have been to give a brief overview of the various ways to access extended memory, perhaps these details could have their own \"Memory mapping\" section somewhere else?","type":"text"}]}]}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"The C65's MAP instruction","type":"text"}]},{"type":"paragraph","content":[{"text":"Taken from c65 manual: 2.3.4. Memory Mapper","type":"text"}]},{"type":"paragraph","content":[{"text":"The microprocessor core is actually a C4502R1 with some additional instructions, used to operate the memory mapper.","type":"text"}]},{"type":"paragraph","content":[{"text":"The former AUG (augment) opcode has been changed to MAP (mapper), and the former NOP (no-operation) has been changed to EOM (end-of-mapping-sequence).","type":"text"}]},{"type":"paragraph","content":[{"text":"The 4510 memory mapper allows the microprocessor to access up to 1 megabyte of memory. Here's how. The 6502 microprocessor can only access 64K bytes of memory because it only uses addresses of 16 bit's. The 4502 is not different, nor is the 4510. But the 4510 memory mapper allows these addresses to be redirected to new physical addresses to access different parts of a much larger memory, within the 64K byte confinement window.","type":"text"}]},{"type":"paragraph","content":[{"text":"The 64K window has been divided into eight blocks, and two regions, with four blocks in each region. Blocks 0 through 3 are in the \"lower\" region, and blocks 4 through 7 are in the \"upper\" region, as shown...","type":"text"}]},{"type":"codeBlock","content":[{"text":" +- +-----------+FFFF\n | | BLK 7 |\n | +-----------+E000\n | | BLK 6 |\n UPPER REGION -+ +-----------+C000\n | | BLK 5 |\n | +-----------+A000\n | | BLK 4 |\n +- +-----------+8000\n | | BLK 3 |\n | +-----------+6000\n | | BLK 2 |\n LOWER REGION -+ +-----------+4000\n | | BLK 1 |\n | +-----------+2000\n | | BLK 0 |\n +- +-----------+","type":"text"}]},{"type":"paragraph","content":[{"text":"Each block can be programmed to be \"mapped\", or \"non-mapped\" via bits in the mapper's \"mask\" registers. NON-MAPPED means, simply, address out equals address in. Therefore, there are still only 64K","type":"text"},{"type":"hardBreak"},{"text":"bytes of non-mapped memory. MAPPED means that address out equals address in plus some offset. The offset is programmed via the mapper's \"offset\" registers.","type":"text"}]},{"type":"paragraph","content":[{"text":"There are two \"offset\" registers. One is for the lower region, and one is for the upper region.","type":"text"}]},{"type":"paragraph","content":[{"text":"The low-order 6 addresses are never mapped. The offsets are only added to the 12 high-order addresses. This means the smallest unit you can map to is 256 bytes, or one page.","type":"text"}]},{"type":"paragraph","content":[{"text":"The 4510 has an output (NOMAP) which lets the outside world know when the processor is accessing mapped (0) or non-mapped (1) address. This is useful for systems where you may want I/O devices to be at fixed (non-mapped) addresses, and only memory at mapped addresses.","type":"text"}]},{"type":"paragraph","content":[{"text":"It is possible, and likely, to have mapped, and unmapped memory at the same physical address. And, with offset registers set to zero, mapped addresses will match unmapped ones. The only difference is the NOMAP signal to tell whether the address is mapped or unmapped.","type":"text"}]},{"type":"paragraph","content":[{"text":"To program the mapper, the operating system must load the A, X, Y, and Z registers with the following information, and execute a MAP opcode.","type":"text"}]},{"type":"codeBlock","content":[{"text":" Mapper Register Data\n\n 7 6 5 4 3 2 1 0 BIT\n +-------+-------+-------+-------+-------+-------+-------+-------+\n | LOWER | LOWER | LOWER | LOWER | LOWER | LOWER | LOWER | LOWER | A\n | OFF15 | OFF14 | OFF13 | OFF12 | OFF11 | OFF10 | OFF9 | OFF8 |\n +-------+-------+-------+-------+-------+-------+-------+-------+\n | MAP | MAP | MAP | MAP | LOWER | LOWER | LOWER | LOWER | X\n | BLK3 | BLK2 | BLK1 | BLK0 | OFF19 | OFF18 | OFF17 | OFF16 |\n +-------+-------+-------+-------+-------+-------+-------+-------+\n | UPPER | UPPER | UPPER | UPPER | UPPER | UPPER | UPPER | UPPER | Y\n | OFF15 | OFF14 | OFF13 | OFF12 | OFF11 | OFF10 | OFF9 | OFF8 |\n +-------+-------+-------+-------+-------+-------+-------+-------+\n | MAP | MAP | MAP | MAP | UPPER | UPPER | UPPER | UPPER | Z\n | BLK7 | BLK6 | BLK5 | BLK4 | OFF19 | OFF18 | OFF17 | OFF16 |\n +-------+-------+-------+-------+-------+-------+-------+-------+","type":"text"}]},{"type":"paragraph","content":[{"text":"After executing the MAP opcode, all interrupts are inhibited. This is done to allow the operating system is complete a mapping sequence without fear of getting an interrupt. An interrupt occurring before the proper stack-pointer is set will cause return address data to be written to an undesired area.","type":"text"}]},{"type":"paragraph","content":[{"text":"Upon completing the mapping sequence, the operating system must remove the interrupt inhibit by executing a EOM (formerly NOP) opcode. Note that application software may execute NOPs with no effect.","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"The MEGA65's MAP instruction","type":"text"}]},{"type":"paragraph","content":[{"text":"My thoughts from the ","type":"text"},{"type":"inlineCard","attrs":{"url":"http://forum64.de"}},{"text":" thread:","type":"text"}]},{"type":"paragraph","content":[{"text":"Both examples I tried to dissect in this thread were actually calling MAP twice. The first MAP call was selecting the megabyte to use for the offset, while the 2nd MAP call was deciding where within that selected megabyte to treat as our absolute offset.","type":"text"}]},{"type":"paragraph","content":[{"text":"Here's my diagram for the megabyte selector register usage:","type":"text"}]},{"type":"codeBlock","content":[{"text":"MEGA65 Megabyte Selector Register Data\n\n 7 6 5 4 3 2 1 0 BIT\n +-------+-------+-------+-------+-------+-------+-------+-------+\n | LOWER | LOWER | LOWER | LOWER | LOWER | LOWER | LOWER | LOWER | A\n | OFF27 | OFF26 | OFF25 | OFF24 | OFF23 | OFF22 | OFF21 | OFF20 |\n | | | | | | | | |\n +-------+-------+-------+-------+-------+-------+-------+-------+\n | MEGABYTE SELECTOR TOKEN (0x0F) | X\n | | | | | | | | |\n | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |\n +-------+-------+-------+-------+-------+-------+-------+-------+\n | UPPER | UPPER | UPPER | UPPER | UPPER | UPPER | UPPER | UPPER | Y\n | OFF27 | OFF26 | OFF25 | OFF24 | OFF23 | OFF22 | OFF21 | OFF20 |\n | | | | | | | | |\n +-------+-------+-------+-------+-------+-------+-------+-------+\n | MEGABYTE SELECTOR TOKEN (0x0F) | Z\n | | | | | | | | |\n | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |\n +-------+-------+-------+-------+-------+-------+-------+-------+","type":"text"}]},{"type":"paragraph","content":[{"text":"Note that:","type":"text"}]},{"type":"paragraph","content":[{"text":"A-register will contain bits 20-27 of your MAPL offset (which equates to the megabyte selected)","type":"text"}]},{"type":"paragraph","content":[{"text":"X-register will contain an 0x0F token value, to indicate that we intend to make a 'megabyte selection' in the A-register","type":"text"}]},{"type":"paragraph","content":[{"text":"Y-register will contain bits 20-27 of your MAPH offset (which equates to the megabyte selected)","type":"text"}]},{"type":"paragraph","content":[{"text":"Z-register will contain an 0x0F token value, to indicate that we intend to make a 'megabyte selection' in the Y-register","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Precedence","type":"text"}]},{"type":"paragraph","content":[{"text":"Gabor had some info on this in the thread:","type":"text"}]},{"type":"paragraph","content":[{"text":"Just we must be careful here, even C64-way of \"MMU\" (CPU port @ addr 0/1) results in CPU_address - physical_address translation, just it's different than the one done initiated by the MAP instruction ... And again, VIC-III ROM mapping is another layer, which overrides everything. So in order of priority:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"if CPU address refers to a memory area subject of VIC-III ROM mapping, ","type":"text"},{"text":"AND","type":"text","marks":[{"type":"em"}]},{"text":" $D030 VIC-III register instructs the mapping actually, then the physical address is calculated according this scheme.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"if the previous condition does not apply, 8K block of the CPU address is checked if it's set to '1' (mapped) or '0' (not mapped). If mapped, then the CPU address is added to an offset (\"upper\" offset if the CPU address is the upper 32K, \"lower\" offset if the lower 32K) but excluding the lower 8 bits of the CPU address which is \"pass-through\". The generated address will be the physical address for the access at system level.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"if even the previous condition does not apply (ie, not VIC-III ROM \"mapped\", and 8K memory block is marked as not-mapped by MAP instruction), then the address is subject of the C64-style translation only, so it's done as it would be a Commodore 64, with CPU I/O port @ 0/1. Still, the result in physical addresses is different than a C64, since the construction of the machine is different, but from user point of view at least (what the program \"sees\") it's the same process.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"This also means, that if you want to access I/O area at $D000, it can be done to set non-mapped for that block via MAP instruction, and set 0/1 CPU I/O port which enables the I/O area. This is the only way done by the CPU you can access I/O on C65 (you can do it via DMA though, but that's DIFFERENT, since DMA does not apply the CPU's memory mapping!!!!!!!!!). On M65, the situation can be resolved other way too though (which is not possible on C65). On M65, the actual I/O area (areas ... since there are some, for each I/O mode, let it be VIC-II, VIC-III or VIC-IV ... according to the VIC \"key\" register) is for real, can be seen as a part of the physical address space as well, though, for that you must either use extended MAP functionality to set the \"megabyte slice\" for the mapping, or use can instruct extended DMA stuff to address it, or you can use M65's linear addressing mode to generate direct physical address by the CPU itself, without any MMU scheme or such applied. But these are M65-specific, and cannot be used on C65 (you can still use C65 to set DMA to address the I/O space ","type":"text"},{"text":"only","type":"text","marks":[{"type":"em"}]},{"text":" regardless of anything other)","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Mapping Arithmetic","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Gabor's terminology/formula clicked for me:","type":"text"}]}]}]},{"type":"codeBlock","content":[{"text":"Physical Address = CPU Address + Offset","type":"text"}]},{"type":"paragraph","content":[{"text":"Gabor elaborated in the ","type":"text"},{"type":"inlineCard","attrs":{"url":"http://forum64.de"}},{"text":" thread:","type":"text"}]},{"type":"paragraph","content":[{"text":"Actually I \"formula\" should be (for MAP, but do not forget that a cpu_address may be not MAPed, or VIC-III ROM mapping overrides this, or you bypass this address translation totally with \"linear address mode\" etc):","type":"text"}]},{"type":"paragraph","content":[{"text":"physical_address = (((map_offset << 8) + cpu_address) & $FFFFF) | (megabyte_selection << 20)","type":"text"}]},{"type":"paragraph","content":[{"text":"So, \"map_offset\" is chosen from the \"lower\" or \"upper\" offset based on the highest bit of the CPU address (thus lower or upper 32K). Since the offset does not represents the lower 8 bits, I used the \"<<\" shift operation for offset. The cpu_address is added to the map_offset, and the result is truncated to fit into 1 mbyte (ie, 20 bits, that is the \"& $FFFFF\" part). And at last, the upper 8 bits of the physical address is come from the \"mbyte_selection (thus the \"<< 20\") while the lower 20 bits from the previous explanation.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Interpreting the physical address","type":"text"}]},{"type":"paragraph","content":[{"text":"In the C64 world, we've only ever concerned ourselves with 16-bit addresses to span across 64 kilobytes of memory (0000-FFFF).","type":"text"}]},{"type":"paragraph","content":[{"text":"In the C65 world, we now concern ourselves with 20-bit addresses to span across 1 megabyte of memory (00000-FFFFF). From the perspective of the C65 manual, this upper nibble gets referred to as a BANK number (ranging from 0-15), with each BANK number referring to a unique block of 64kb within this 1 megabyte address-space.","type":"text"}]},{"type":"paragraph","content":[{"text":"In the MEGA65 world, we now concern ourselves with 28-bit addresses to span across potentially 256 megabytes of memory (0000000-FFFFFFF). From the perspective of MEGA65 literature, these upper 8-bits are referred to as the MEGABYTE SELECTION (ranging from 0-255), with each MEGABYTE SELECTION number referring to a unique block of 1mb within the 256mb address-space.","type":"text"}]},{"type":"paragraph","content":[{"text":"Here is an example breaking down how terms like \"Megabyte selection\" and \"Bank\" selection relate to the following physical address:","type":"text"}]},{"type":"codeBlock","content":[{"text":" +----- MEGABYTE SELECTION\n |\n | +--- BANK\n | |\n$FFDE800\n\nBank = $D\n\nMegabyte-selection = $FF","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Usage of MAP for the MEGA65","type":"text"}]},{"type":"paragraph","content":[{"text":"A walkthrough of an example that demonstrates all 3 MAP calls mentioned in the appendix:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"disabling of mapping,","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"megabyte selection,","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"offset + 8KB block selection","type":"text"}]}]}]},{"type":"paragraph"}],"version":1}