Been doing some digging into how the uart monitor works currently.
Will paste a few ascii diagrams I was accumulating on how the components work together…
Main Components
+--------------------------------------------------------------------------------------------+ | machine.vhdl | | | | +------------------------------------------------------------------------------------+ | | | monitor_top.v = uart_monitor | | | | | | | | +--------------+ | | | | | monitor_ctrl | | | | | +--------------+ | | | | | | | | +--------------+ | | | | | monitor_bus | | | | | +--------------+ | | | | 1024 x 16 bytes 1024 x 8 bytes 16 x 8 bytes | | | | +--------------+ +---------------+ +---------------+ +--------------+ | | | | | monitor_mem | | asym_ram_sdp | | asym_ram_sdp | | asym_ram_sdp | | | | | | (monitor.a65)| | (historyram0) | | (historyram1) | | (cpustateram)| | | | | +--------------+ +---------------+ +---------------+ +--------------+ | | | | | | | | +--------------+ | | | | | cpu6502 | | | | | +--------------+ | | | | | | | +------------------------------------------------------------------------------------+ | | | +--------------------------------------------------------------------------------------------+
historyram0
+-------------------+
clkA | | clkB
-------> <-------
| |
weA | | enaB
------> <-------
| |
enaA | |
------> |
| |
diA[127:0] | historyram0 | doB[7:0]
-------------> --------------->
| |
addrA[9:0] | | addrB[13:0]
------------> <--------------
| |
+-------------------+
cpustateram
+-------------------+
(clock) clkA | | clkB (clock)
-------> <-------
| |
(cpu_state_write) weA | | enaB (1)
------> <-------
| |
(1) enaA | |
------> |
{ | |
(0 [15:0]) | |
(monitor_cpu_state[15:0]) | |
(monitor_memory_access_address[31:0])| |
} --> diA[63:0] | cpustateram | doB[7:0] (cpu_state_rdata[7:0])
-------------> --------------->
| |
(cpu_state_write_index) addrA[3:0] | | addrB[6:0] (cpu_address_next[6:0])
------------> <--------------
| |
+-------------------+
Signals relating to cpustateram
+--------------------------------------------------------------------+
| monitor_top.v / uart_monitor |
monitor_cpu_state[15:0] | |
------------------------> |
| |
monitor_memory_access_address[31:0] | |
------------------------------------> |
| +----------------+ |
| | monitorctrl | |
| (monitor_cpu_state[15:8])| | |
| cpu_state[7:0] | | |
| -----------------------> | |
| | | |
| cpu_state_write | | |
| <----------------- | |
| | | |
| cpu_state_write_index | | |
| <---------------------- | |
| | | |
| +----------------+ |
| |
| +----------------+ |
| (cpu_state_rdata) | monitorbus | |
| cpu_state | | |
| ----------------> | |
| | | |
| (cpu_address_next[15:0]) | | |
| cpu_address[15:0] | | |
| ----------------> | |
| | | |
| (cpu_di) | | |
| read_data[7:0] | | |
| <--------------- | |
| +----------------+ |
| |
| +----------------+ |
| | cpu6502 | |
| (cpu_address_next[15:0]) | (monitorcpu) | |
| address_next[15:0] | | |
| <------------------- | |
| | | |
| (cpu_di) | | |
| data_i[7:0] | | |
| --------------> | |
| +----------------+ |
| |
+--------------------------------------------------------------------+